Algebraic circuits
Lax461425.Circuits · concepts/Lax461425/Circuits.lean · lax-461425
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Definition
An algebraic circuit over a commutative ring with variables from a set is a finite directed acyclic graph whose input gates are labelled by variables or constants of and whose internal gates are labelled by or . We allow unbounded fan-in and parallel wires: the number of wires from a gate to a gate is the multiplicity , and is a child of if . Input gates have no children. There is a distinguished output gate, and every gate lies on a path to it.
Every gate computes a polynomial : an input gate computes its label, and
if is a sum or a product gate, respectively, so that wires are counted with multiplicity and empty sums and products are and . The circuit computes the polynomial of its output gate. Formally, "the gate computes " is defined inductively by these rules, so that exactly the polynomials obtained by evaluating the circuit bottom-up are computed. Every gate computes exactly one polynomial; the values at children with do not contribute.
The size of a circuit is the number of its gates and wires, counting multiplicities. A path of length is a sequence of gates such that is a child of for all . The depth is the maximum length of a path. Since every gate lies on a path to the output gate, this is the maximum number of wires on a path from the output gate to a gate without children, e.g. an input gate.
A circuit is reduced if no two distinct input gates have the same label and no two distinct internal gates have the same label and the same multiset of children, i.e. the same multiplicities .
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| 1 | import Mathlib.Algebra.MvPolynomial.Basic |
| 2 | import Mathlib.Data.Set.Card |
| 3 | import Mathlib.Logic.Relation |
| 4 | |
| 5 | /-! |
| 6 | --- |
| 7 | title: Algebraic circuits |
| 8 | type: definition |
| 9 | --- |
| 10 | An *algebraic circuit* over a commutative ring with variables from a set is a |
| 11 | finite directed acyclic graph whose input gates are labelled by variables or constants of |
| 12 | and whose internal gates are labelled by or . We allow unbounded fan-in |
| 13 | and parallel wires: the number of wires from a gate to a gate is the *multiplicity* |
| 14 | , and is a *child* of if . Input gates have no |
| 15 | children. There is a distinguished output gate, and every gate lies on a path to it. |
| 16 | |
| 17 | Every gate computes a polynomial : an input gate computes its label, |
| 18 | and |
| 19 | |
| 20 | |
| 21 | |
| 22 | if is a sum or a product gate, respectively, so that wires are counted with multiplicity |
| 23 | and empty sums and products are and . The circuit *computes* the polynomial of its |
| 24 | output gate. Formally, "the gate computes " is defined inductively by these rules, so |
| 25 | that exactly the polynomials obtained by evaluating the circuit bottom-up are computed. Every |
| 26 | gate computes exactly one polynomial; the values at children with do not |
| 27 | contribute. |
| 28 | |
| 29 | The *size* of a circuit is the number of its gates and wires, counting multiplicities. A |
| 30 | *path* of length is a sequence of gates such that is a child of |
| 31 | for all . The *depth* is the maximum length of a path. Since every gate lies on a |
| 32 | path to the output gate, this is the maximum number of wires on a path from the output gate to |
| 33 | a gate without children, e.g. an input gate. |
| 34 | |
| 35 | A circuit is *reduced* if no two distinct input gates have the same label and no two distinct |
| 36 | internal gates have the same label and the same multiset of children, i.e. the same |
| 37 | multiplicities . |
| 38 | -/ |
| 39 | |
| 40 | namespace Lax461425.Circuits |
| 41 | |
| 42 | /-- The label of a gate: a variable, a constant, or one of the operations `+` and `×`. -/ |
| 43 | inductive GateLabel (V K : Type*) where |
| 44 | | var (x : V) |
| 45 | | const (c : K) |
| 46 | | add |
| 47 | | mul |
| 48 | |
| 49 | namespace GateLabel |
| 50 | |
| 51 | variable {V K : Type*} |
| 52 | |
| 53 | /-- Input gates are the gates labelled by a variable or a constant. -/ |
| 54 | def IsInput : GateLabel V K → Prop |
| 55 | | var _ => True |
| 56 | | const _ => True |
| 57 | | add => False |
| 58 | | mul => False |
| 59 | |
| 60 | /-- Rename the variable of a label along `π`, keeping constants and operations fixed. -/ |
| 61 | def map (π : V → V) : GateLabel V K → GateLabel V K |
| 62 | | var x => var (π x) |
| 63 | | const c => const c |
| 64 | | add => add |
| 65 | | mul => mul |
| 66 | |
| 67 | end GateLabel |
| 68 | |
| 69 | /-- An algebraic circuit with variables `V` and constants from `K`. -/ |
| 70 | structure Circuit (V K : Type*) where |
| 71 | /-- The finite set of gates. -/ |
| 72 | Gate : Type |
| 73 | [fintypeGate : Fintype Gate] |
| 74 | /-- The label of each gate. -/ |
| 75 | label : Gate → GateLabel V K |
| 76 | /-- `wire g h` is the multiplicity of the wire from `h` into `g`. -/ |
| 77 | wire : Gate → Gate → ℕ |
| 78 | /-- The output gate. -/ |
| 79 | out : Gate |
| 80 | /-- Input gates have no children. -/ |
| 81 | wire_eq_zero_of_isInput : ∀ g h, (label g).IsInput → wire g h = 0 |
| 82 | /-- There is no directed cycle. -/ |
| 83 | acyclic : ∀ g, ¬ Relation.TransGen (fun h g => 0 < wire g h) g g |
| 84 | /-- Every gate lies on a path to the output gate. -/ |
| 85 | reaches_out : ∀ g, Relation.ReflTransGen (fun h g => 0 < wire g h) g out |
| 86 | |
| 87 | attribute [instance] Circuit.fintypeGate |
| 88 | |
| 89 | namespace Circuit |
| 90 | |
| 91 | variable {V K : Type*} (C : Circuit V K) |
| 92 | |
| 93 | /-- `C.ComputesAt g p`: the gate `g` computes the polynomial `p`. A sum or product gate |
| 94 | computes the sum or product of polynomials `q h` computed at its children `h`, counted with |
| 95 | multiplicity. -/ |
| 96 | inductive ComputesAt [CommSemiring K] (C : Circuit V K) : C.Gate → MvPolynomial V K → Prop |
| 97 | | var {g : C.Gate} {x : V} : C.label g = .var x → C.ComputesAt g (MvPolynomial.X x) |
| 98 | | const {g : C.Gate} {c : K} : C.label g = .const c → C.ComputesAt g (MvPolynomial.C c) |
| 99 | | add {g : C.Gate} (q : C.Gate → MvPolynomial V K) : C.label g = .add → |
| 100 | (∀ h, 0 < C.wire g h → C.ComputesAt h (q h)) → C.ComputesAt g (∑ h, C.wire g h • q h) |
| 101 | | mul {g : C.Gate} (q : C.Gate → MvPolynomial V K) : C.label g = .mul → |
| 102 | (∀ h, 0 < C.wire g h → C.ComputesAt h (q h)) → C.ComputesAt g (∏ h, q h ^ C.wire g h) |
| 103 | |
| 104 | /-- The circuit computes the polynomial `p` at its output gate. -/ |
| 105 | def Computes [CommSemiring K] (p : MvPolynomial V K) : Prop := |
| 106 | C.ComputesAt C.out p |
| 107 | |
| 108 | /-- The number of gates plus the number of wires, counted with multiplicity. -/ |
| 109 | def size : ℕ := |
| 110 | Fintype.card C.Gate + ∑ g, ∑ h, C.wire g h |
| 111 | |
| 112 | /-- The gates `p 0, …, p m` form a path: each `p (i + 1)` is a child of `p i`. -/ |
| 113 | def IsPath {m : ℕ} (p : Fin (m + 1) → C.Gate) : Prop := |
| 114 | ∀ i : Fin m, 0 < C.wire (p i.castSucc) (p i.succ) |
| 115 | |
| 116 | /-- The maximum length of a path. -/ |
| 117 | noncomputable def depth : ℕ := |
| 118 | sSup {m | ∃ p : Fin (m + 1) → C.Gate, C.IsPath p} |
| 119 | |
| 120 | /-- No two distinct input gates carry the same label, and no two distinct internal gates carry |
| 121 | the same label and the same multiset of children. -/ |
| 122 | def IsReduced : Prop := |
| 123 | (∀ g g', (C.label g).IsInput → C.label g = C.label g' → g = g') ∧ |
| 124 | ∀ g g', ¬ (C.label g).IsInput → C.label g = C.label g' → C.wire g = C.wire g' → g = g' |
| 125 | |
| 126 | end Circuit |
| 127 | |
| 128 | end Lax461425.Circuits |
| 129 |
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