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Algebraic circuits

Lax461425.Circuits · concepts/Lax461425/Circuits.lean · lax-461425

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    Natural Language Statement

    Definition

    An algebraic circuit over a commutative ring K\mathbb{K} with variables from a set VV is a finite directed acyclic graph whose input gates are labelled by variables or constants of K\mathbb{K} and whose internal gates are labelled by ++ or ×\times. We allow unbounded fan-in and parallel wires: the number of wires from a gate hh to a gate gg is the multiplicity m(g,h)∈Nm(g,h) \in \mathbb{N}, and hh is a child of gg if m(g,h)>0m(g,h) > 0. Input gates have no children. There is a distinguished output gate, and every gate lies on a path to it.

    Every gate gg computes a polynomial pg∈K[V]p_g \in \mathbb{K}[V]: an input gate computes its label, and

    pg=∑hm(g,h) phorpg=∏hphm(g,h)p_g = \sum_h m(g,h)\, p_h \quad\text{or}\quad p_g = \prod_h p_h^{m(g,h)}

    if gg is a sum or a product gate, respectively, so that wires are counted with multiplicity and empty sums and products are 00 and 11. The circuit computes the polynomial of its output gate. Formally, "the gate gg computes pp" is defined inductively by these rules, so that exactly the polynomials obtained by evaluating the circuit bottom-up are computed. Every gate computes exactly one polynomial; the values php_h at children hh with m(g,h)=0m(g,h) = 0 do not contribute.

    The size of a circuit is the number of its gates and wires, counting multiplicities. A path of length mm is a sequence of gates g0,…,gmg_0, \dots, g_m such that gi+1g_{i+1} is a child of gig_i for all i<mi < m. The depth is the maximum length of a path. Since every gate lies on a path to the output gate, this is the maximum number of wires on a path from the output gate to a gate without children, e.g. an input gate.

    A circuit is reduced if no two distinct input gates have the same label and no two distinct internal gates have the same label and the same multiset of children, i.e. the same multiplicities m(g,⋅)m(g, \cdot).

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    1import Mathlib.Algebra.MvPolynomial.Basic
    2import Mathlib.Data.Set.Card
    3import Mathlib.Logic.Relation
    4
    5/-!
    6---
    7title: Algebraic circuits
    8type: definition
    9---
    10An *algebraic circuit* over a commutative ring K\mathbb{K} with variables from a set VV is a
    11finite directed acyclic graph whose input gates are labelled by variables or constants of
    12K\mathbb{K} and whose internal gates are labelled by ++ or ×\times. We allow unbounded fan-in
    13and parallel wires: the number of wires from a gate hh to a gate gg is the *multiplicity*
    14m(g,h)∈Nm(g,h) \in \mathbb{N}, and hh is a *child* of gg if m(g,h)>0m(g,h) > 0. Input gates have no
    15children. There is a distinguished output gate, and every gate lies on a path to it.
    16
    17Every gate gg computes a polynomial pg∈K[V]p_g \in \mathbb{K}[V]: an input gate computes its label,
    18and
    19
    20pg=∑hm(g,h) phorpg=∏hphm(g,h)p_g = \sum_h m(g,h)\, p_h \quad\text{or}\quad p_g = \prod_h p_h^{m(g,h)}
    21
    22if gg is a sum or a product gate, respectively, so that wires are counted with multiplicity
    23and empty sums and products are 00 and 11. The circuit *computes* the polynomial of its
    24output gate. Formally, "the gate gg computes pp" is defined inductively by these rules, so
    25that exactly the polynomials obtained by evaluating the circuit bottom-up are computed. Every
    26gate computes exactly one polynomial; the values php_h at children hh with m(g,h)=0m(g,h) = 0 do not
    27contribute.
    28
    29The *size* of a circuit is the number of its gates and wires, counting multiplicities. A
    30*path* of length mm is a sequence of gates g0,…,gmg_0, \dots, g_m such that gi+1g_{i+1} is a child of
    31gig_i for all i<mi < m. The *depth* is the maximum length of a path. Since every gate lies on a
    32path to the output gate, this is the maximum number of wires on a path from the output gate to
    33a gate without children, e.g. an input gate.
    34
    35A circuit is *reduced* if no two distinct input gates have the same label and no two distinct
    36internal gates have the same label and the same multiset of children, i.e. the same
    37multiplicities m(g,⋅)m(g, \cdot).
    38-/
    39
    40namespace Lax461425.Circuits
    41
    42/-- The label of a gate: a variable, a constant, or one of the operations `+` and `×`. -/
    43inductive GateLabel (V K : Type*) where
    44 | var (x : V)
    45 | const (c : K)
    46 | add
    47 | mul
    48
    49namespace GateLabel
    50
    51variable {V K : Type*}
    52
    53/-- Input gates are the gates labelled by a variable or a constant. -/
    54def IsInput : GateLabel V K → Prop
    55 | var _ => True
    56 | const _ => True
    57 | add => False
    58 | mul => False
    59
    60/-- Rename the variable of a label along `π`, keeping constants and operations fixed. -/
    61def map (π : V → V) : GateLabel V K → GateLabel V K
    62 | var x => var (π x)
    63 | const c => const c
    64 | add => add
    65 | mul => mul
    66
    67end GateLabel
    68
    69/-- An algebraic circuit with variables `V` and constants from `K`. -/
    70structure Circuit (V K : Type*) where
    71 /-- The finite set of gates. -/
    72 Gate : Type
    73 [fintypeGate : Fintype Gate]
    74 /-- The label of each gate. -/
    75 label : Gate → GateLabel V K
    76 /-- `wire g h` is the multiplicity of the wire from `h` into `g`. -/
    77 wire : Gate → Gate → ℕ
    78 /-- The output gate. -/
    79 out : Gate
    80 /-- Input gates have no children. -/
    81 wire_eq_zero_of_isInput : ∀ g h, (label g).IsInput → wire g h = 0
    82 /-- There is no directed cycle. -/
    83 acyclic : ∀ g, ¬ Relation.TransGen (fun h g => 0 < wire g h) g g
    84 /-- Every gate lies on a path to the output gate. -/
    85 reaches_out : ∀ g, Relation.ReflTransGen (fun h g => 0 < wire g h) g out
    86
    87attribute [instance] Circuit.fintypeGate
    88
    89namespace Circuit
    90
    91variable {V K : Type*} (C : Circuit V K)
    92
    93/-- `C.ComputesAt g p`: the gate `g` computes the polynomial `p`. A sum or product gate
    94computes the sum or product of polynomials `q h` computed at its children `h`, counted with
    95multiplicity. -/
    96inductive ComputesAt [CommSemiring K] (C : Circuit V K) : C.Gate → MvPolynomial V K → Prop
    97 | var {g : C.Gate} {x : V} : C.label g = .var x → C.ComputesAt g (MvPolynomial.X x)
    98 | const {g : C.Gate} {c : K} : C.label g = .const c → C.ComputesAt g (MvPolynomial.C c)
    99 | add {g : C.Gate} (q : C.Gate → MvPolynomial V K) : C.label g = .add →
    100 (∀ h, 0 < C.wire g h → C.ComputesAt h (q h)) → C.ComputesAt g (∑ h, C.wire g h • q h)
    101 | mul {g : C.Gate} (q : C.Gate → MvPolynomial V K) : C.label g = .mul →
    102 (∀ h, 0 < C.wire g h → C.ComputesAt h (q h)) → C.ComputesAt g (∏ h, q h ^ C.wire g h)
    103
    104/-- The circuit computes the polynomial `p` at its output gate. -/
    105def Computes [CommSemiring K] (p : MvPolynomial V K) : Prop :=
    106 C.ComputesAt C.out p
    107
    108/-- The number of gates plus the number of wires, counted with multiplicity. -/
    109def size : ℕ :=
    110 Fintype.card C.Gate + ∑ g, ∑ h, C.wire g h
    111
    112/-- The gates `p 0, …, p m` form a path: each `p (i + 1)` is a child of `p i`. -/
    113def IsPath {m : ℕ} (p : Fin (m + 1) → C.Gate) : Prop :=
    114 ∀ i : Fin m, 0 < C.wire (p i.castSucc) (p i.succ)
    115
    116/-- The maximum length of a path. -/
    117noncomputable def depth : ℕ :=
    118 sSup {m | ∃ p : Fin (m + 1) → C.Gate, C.IsPath p}
    119
    120/-- No two distinct input gates carry the same label, and no two distinct internal gates carry
    121the same label and the same multiset of children. -/
    122def IsReduced : Prop :=
    123 (∀ g g', (C.label g).IsInput → C.label g = C.label g' → g = g') ∧
    124 ∀ g g', ¬ (C.label g).IsInput → C.label g = C.label g' → C.wire g = C.wire g' → g = g'
    125
    126end Circuit
    127
    128end Lax461425.Circuits
    129

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